Three dimensional (3D) memory technology, using pillar access devices and other methods, is evolving in the memory industry. Use of 3D technology enables higher density for the memory array core of a memory device with memory cells arranged vertically. Such structures provide a number of levels of arrays of memory cells, where the levels arranged in a stack may be referred to as decks. However, periphery logic, such as redundancy repair fuses or other logic is built using conventional two dimensional (2D) planar transistors. Some recent designs use a fuse array to store repair information. With 3D vertically stacked memory cores using more repair elements, this configuration increases the number of fuse latches in each bank. For this reason, redundancy fuses will increasingly occupy a relatively larger percentage of 2D die area than for 2D planar array core designs. Going forward this trend will continue as 3D stacking is extended from a 2 deck structure to a 4 deck structure, an 8 deck structure, etc.